[all-commits] [llvm/llvm-project] 3a272d: [SVE][CodeGen] Use splice instruction when lowerin...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a272d1eaf2679f9fdd7eb49b4e3250d31f0d9a3
      https://github.com/llvm/llvm-project/commit/3a272d1eaf2679f9fdd7eb49b4e3250d31f0d9a3
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-01-11 (Tue, 11 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

  Log Message:
  -----------
  [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

For certain negative indices passed to the VECTOR_SPLICE operation
we can actually directly use the SVE splice instruction by creating
the appropriate predicate. The predicate needs to be constructed in
such a way that all but the last -idx elements are false. We can do
this efficiently using a combination of 'ptrue' (with the appropriate
fixed pattern, e.g. vl1, vl2, etc.) and 'rev'. The advantage of using
these instructions to generate the predicate is they do not set any
flags, unlike the whilelo instruction. This is critical when the splice
operation is in a loop, since we want MachineLICM to hoist the
predicate generation out of the loop.

Differential Revision: https://reviews.llvm.org/D115863