[all-commits] [llvm/llvm-project] 51497d: [IR] Change vector.splice intrinsic to reject out-...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51497dc0b20179eb145820cb8f651f026960de08
      https://github.com/llvm/llvm-project/commit/51497dc0b20179eb145820cb8f651f026960de08
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-01-11 (Tue, 11 Jan 2022)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    A llvm/test/Verifier/invalid-splice.ll

  Log Message:
  -----------
  [IR] Change vector.splice intrinsic to reject out-of-bounds indices

I've changed the definition of the experimental.vector.splice
instrinsic to reject indices that are known to be or possibly
out-of-bounds. In practice, this means changing the definition so that
the index is now only valid in the range [-VL, VL-1] where VL is the
known minimum vector length. We use the vscale_range attribute to
take the minimum vscale value into account so that we can permit
more indices when the attribute is present.

The splice intrinsic is currently only ever generated by the vectoriser,
which will never attempt to splice vectors with out-of-bounds values.
Changing the definition also makes things simpler for codegen since we
can always assume that the index is valid.

This patch was created in response to review comments on D115863

Differential Revision: https://reviews.llvm.org/D115933