[all-commits] [llvm/llvm-project] 9ea772: [RISCV] Block vmsgeu.vi with 0 immediate in Isel

ZCBing via All-commits all-commits at lists.llvm.org
Mon Jan 10 19:05:05 PST 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ea772ff81eb421ae521345b33d844c892a6725c
      https://github.com/llvm/llvm-project/commit/9ea772ff81eb421ae521345b33d844c892a6725c
  Author: Chenbing.Zheng <Chenbing.Zheng at streamcomputing.com>
  Date:   2022-01-11 (Tue, 11 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

  Log Message:
  -----------
  [RISCV] Block vmsgeu.vi with 0 immediate in Isel

For vmsgeu.vi with 0, we know this is always true. So we can replace
it with vmset.m (unmasked) or vmset.m+vmand.mm (masked).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D116584




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