[all-commits] [llvm/llvm-project] bd653f: [RISCV] Use shift for zero extension when Zbb and ...

[Haocong Lu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd653f6406e7ff59e318551c7288a0b5a468b88e
      https://github.com/llvm/llvm-project/commit/bd653f6406e7ff59e318551c7288a0b5a468b88e
  Author: Haocong.Lu <Haocong.Lu at streamcomputing.com>
  Date:   2022-01-11 (Tue, 11 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/alu16.ll
    A llvm/test/CodeGen/RISCV/and.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled

Now AND is used for zero extension when both Zbb and Zbp are not enabled.
It may be better to use shift operation if the trailing ones mask exceeds simm12.

This patch optimzes LUI+ADDI+AND to SLLI+SRLI.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D116720