[all-commits] [llvm/llvm-project] 296e8c: [RISCV] Isel (sra (sext_inreg X, i16), C) -> (srai...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 296e8cae5cdaaf292df00453d15fbd5858d6ea0c
      https://github.com/llvm/llvm-project/commit/296e8cae5cdaaf292df00453d15fbd5858d6ea0c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-01-09 (Sun, 09 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

  Log Message:
  -----------
  [RISCV] Isel (sra (sext_inreg X, i16), C) -> (srai (slli X, (XLen-16), (XLen-16) + C).

Similar for (sra (sext_inreg X, i8), C).

With Zbb, sext_inreg of i8 and i16 are legal for sext.b and sext.h.
This transform makes the Zbb codegen the same as without Zbb. The
shifts are more compressible. This also exposes an opportunity for
CSE with another slli in the i16 sdiv by constant codegen.