[all-commits] [llvm/llvm-project] 6b8362: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b8362eb8dc87be8977e3c1d3a7b2ff35a15898c
      https://github.com/llvm/llvm-project/commit/6b8362eb8dc87be8977e3c1d3a7b2ff35a15898c
  Author: jacquesguan <jacquesguan at me.com>
  Date:   2022-01-10 (Mon, 10 Jan 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
    A llvm/test/MC/RISCV/rvv/invalid-eew.s

  Log Message:
  -----------
  [RISCV] Disable EEW=64 for index values when XLEN=32.

Disable EEW=64 for vector index load/store when XLEN=32.

Differential Revision: https://reviews.llvm.org/D106518