[all-commits] [llvm/llvm-project] f142c4: [RISCV] Set getMinVectorRegisterBitWidth to 16 if ...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f142c45f1e494f8dbdcc1bcf14122d128ac8f3fe
      https://github.com/llvm/llvm-project/commit/f142c45f1e494f8dbdcc1bcf14122d128ac8f3fe
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-01-08 (Sat, 08 Jan 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/SLPVectorizer/RISCV/lit.local.cfg
    A llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll

  Log Message:
  -----------
  [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV

getMinVectorRegisterBitWidth means what vector types is supported in
this target, and actually RISC-V support all fixed length vector types with
vector length less than `getMinRVVVectorSizeInBits`, so set it to 16,
means 2 x i8, that is minimal fixed length vector size in theory.

That also fixed one issue, some testcase migth become non-vectorizable
when `-riscv-v-vector-bits-min` set to larger value, because the vector size is
smaller than `-riscv-v-vector-bits-min`.

For example, following code can vectorize by SLP with
`-riscv-v-vector-bits-min=128` or `-riscv-v-vector-bits-min=256`, but
can't vectorize `-riscv-v-vector-bits-min=512` or larger:

```
void foo(double *da) {
  da[0] = 0;
  da[1] = 1;
  da[2] = 2;
  da[3] = 3;
}
```

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D116534