[all-commits] [llvm/llvm-project] ec4dd8: [RISCV] Use simm5_plus1_nonzero in isel patterns f...
Craig Topper via All-commits
all-commits at lists.llvm.org
Thu Jan 6 08:28:36 PST 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: ec4dd862bf548c157b2c992efe4f10da4f04c4e2
https://github.com/llvm/llvm-project/commit/ec4dd862bf548c157b2c992efe4f10da4f04c4e2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-01-06 (Thu, 06 Jan 2022)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
Log Message:
-----------
[RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics.
The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing
the immediate. To prevent his we had special patterns that provided
alternate lowering for the 0 cases. This relied on tablegen prioritizing
the 0 pattern over the sim5_plus1 range.
This patch introduces simm5_plus1_nonzero that excludes 0. It also
excludes the special case for vmsltu.vi since we can just use
vmsltu.vx and let the 0 be selected to X0.
This is an alternative to some of the changes in D116584.
Reviewed By: Chenbing.Zheng, asb
Differential Revision: https://reviews.llvm.org/D116723
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