[all-commits] [llvm/llvm-project] 2819e5: [Hexagon] Handle instruction selection for select(...

[iajbar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2819e5de42e03f100c9a90c1328465e99d28ee5d
      https://github.com/llvm/llvm-project/commit/2819e5de42e03f100c9a90c1328465e99d28ee5d
  Author: Ikhlas Ajbar <iajbar at quicinc.com>
  Date:   2022-01-05 (Wed, 05 Jan 2022)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
    A llvm/test/CodeGen/Hexagon/select-vector-pred.ll

  Log Message:
  -----------
  [Hexagon] Handle instruction selection for select(I1,Q,Q)

Lower select(I1,Q,Q) by converting vector predicate Q to vector register V,
doing select(I1,V,V), and then converting the resulting V back to Q. Also,
try to avoid creating such situations in the first place.