[all-commits] [llvm/llvm-project] e35a3f: [AArch64] Adding "armv8.8-a" memcpy/memset support.

[Simon Tatham via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e35a3f188f6a33ba63000d4d2b999f341cd57a9f
      https://github.com/llvm/llvm-project/commit/e35a3f188f6a33ba63000d4d2b999f341cd57a9f
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2022-01-05 (Wed, 05 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    A llvm/test/MC/AArch64/armv8.8a-mops.s
    A llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt

  Log Message:
  -----------
  [AArch64] Adding "armv8.8-a" memcpy/memset support.

This family of instructions includes CPYF (copy forward), CPYB (copy
backward), SET (memset) and SETG (memset + initialise MTE tags), with
some sub-variants to indicate whether address translation is done in a
privileged or unprivileged way. For the copy instructions, you can
separately specify the read and write translations (so that kernels
can safely use these instructions in syscall handlers, to memcpy
between the calling process's user-space memory map and the kernel's
own privileged one).

The unusual thing about these instructions is that they write back to
multiple registers, because they perform an implementation-defined
amount of copying each time they run, and write back to _all_ the
address and size registers to indicate how much remains to be done
(and the code is expected to loop on them until the size register
becomes zero). But this is no problem in LLVM - you just define each
instruction to have multiple outputs, multiple inputs, and a set of
constraints tying their register numbers together appropriately.

This commit introduces a special subtarget feature called MOPS (after
the name the spec gives to the CPU id field), which is a dependency of
the top-level 8.8-A feature, and uses that to enable most of the new
instructions. The SETMG instructions also depend on MTE (and the test
checks that).

Differential Revision: https://reviews.llvm.org/D116157