[all-commits] [llvm/llvm-project] 2b1c6d: [Hexagon] Performance regression with b2b

Krzysztof Parzyszek via All-commits all-commits at lists.llvm.org
Tue Jan 4 14:14:03 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b1c6df5a60ab7846974676586b0e3801e919772
  Author: Harsha Jagasia <hjagasia at quicinc.com>
  Date:   2022-01-04 (Tue, 04 Jan 2022)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
    A llvm/test/CodeGen/Hexagon/nbench1.ll

  Log Message:
  [Hexagon] Performance regression with b2b

For code below:
                r7 = addasl(r3,r0,#2)
                r8 = addasl(r3,r2,#2)
                r5 = memw(r3+r0<<#2)
                r6 = memw(r3+r2<<#2)
                p1 = cmp.gtu(r6,r5)
                if (p1.new) memw(r8+#0) = r5
                if (p1.new) memw(r7+#0) = r6
                r0 = mux(p1,r2,r4)


In packetizer, a new packet is created for the cmp instruction since
there arent enough resources in previous packet. Also it is determined
that the cmp stalls by 2 cycles since it depends on the prior load of r5.
In current packetizer implementation, the predicated store is evaluated
for whether it can go in the same packet as compare, and since the compare
stalls, the stall of the predicated store does not matter and it can go in
the same packet as the cmp. However the predicated store will stall for
more cycles because of its dependence on the addasl instruction and to
avoid that stall we can put it in a new packet.

Improve the packetizer to check if an instruction being added to packet
will stall longer than instruction already in packet and if so create a
new packet.

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