[all-commits] [llvm/llvm-project] 8c1e52: [AArch64] Adding "armv8.8-a" BC instruction.

[Simon Tatham via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8c1e520c903e0b7e758f8fbf4f1c3824f0d3efad
      https://github.com/llvm/llvm-project/commit/8c1e520c903e0b7e758f8fbf4f1c3824f0d3efad
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2022-01-03 (Mon, 03 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    A llvm/test/MC/AArch64/armv8.8a-hbc.s
    A llvm/test/MC/Disassembler/AArch64/armv8.8a-hbc.txt

  Log Message:
  -----------
  [AArch64] Adding "armv8.8-a" BC instruction.

This instruction is described in the Arm A64 Instruction Set
Architecture documentation available here:
https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en

FEAT_HBC "Hinted Conditional Branches" is listed in the 2021 A-Profile Architecture Extensions:
https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools/feature-names-for-a-profile

'BC.cc', where 'cc' is any ordinary condition code, is an instruction
that looks exactly like B.cc (the normal conditional branch), except
that bit 4 of the encoding is 1 rather than 0, which hints something
to the branch predictor (specifically, that this branch is expected to
be highly consistent, even though _which way_ it will consistently go
is not known at compile time).

This commit introduces a special subtarget feature for HBC, which is a
dependency of the top-level 8.8-A feature, and uses that to enable the
new BC instruction.

Differential Revision: https://reviews.llvm.org/D116156