[all-commits] [llvm/llvm-project] d00e43: [RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOp...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d00e438cfe7ef6af6654810a34ef461988e93172
      https://github.com/llvm/llvm-project/commit/d00e438cfe7ef6af6654810a34ef461988e93172
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-31 (Fri, 31 Dec 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.

This is similar to what is done for targets that prefer zero extend
where we avoid using a zero extend if the promoted values are sign
extended.

We'll also check for zero extended operands for ugt, ult, uge, and ule when the
target prefers sign extend. This is different than preferring zero extend, where
we only check for sign bits on equality comparisons.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D116421