[all-commits] [llvm/llvm-project] a1c7dd: [RISCV] Support passing scalable vectur values thr...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a1c7ddf9264e21a1f8ef6e118d7041a0166076d1
      https://github.com/llvm/llvm-project/commit/a1c7ddf9264e21a1f8ef6e118d7041a0166076d1
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-12-28 (Tue, 28 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    R llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll

  Log Message:
  -----------
  [RISCV] Support passing scalable vectur values through the stack.

After consuming all vector registers, the scalable vector values will be
passed indirectly. The pointer values will be saved in general
registers. If all general registers are used up, we will report an error to
notify users the compiler does not support passing scalable vector
values through the stack. In this patch, we remove the restriction. After
all general registers are used up, we use the stack to save the
pointers which point to the indirect passed scalable vector values.

Differential Revision: https://reviews.llvm.org/D116310