[all-commits] [llvm/llvm-project] 29475e: [X86] Add scheduler classes for zmm vector reg-reg...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29475e02865b0ecad5f184f413382a68b9040047
      https://github.com/llvm/llvm-project/commit/29475e02865b0ecad5f184f413382a68b9040047
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-12-27 (Mon, 27 Dec 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/lib/Target/X86/X86Schedule.td
    M llvm/lib/Target/X86/X86ScheduleAtom.td
    M llvm/lib/Target/X86/X86ScheduleBdVer2.td
    M llvm/lib/Target/X86/X86ScheduleBtVer2.td
    M llvm/lib/Target/X86/X86ScheduleSLM.td
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bw.s

  Log Message:
  -----------
  [X86] Add scheduler classes for zmm vector reg-reg move instructions

Basic zmm reg-reg moves (with predication) are more port limited than xmm/ymm moves, so we need to add a separate class for them.

We still appear to be missing move-elimination patterns for most of the intel models, which looks to be one of the main diffs for basic codegen analysis between llvm-mca and uops.info

Load/stores are a bit messier and might be better handled as overrides.