[all-commits] [llvm/llvm-project] 5d47e7: [RISCV] Convert whole register copies as the sourc...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d47e7d768951a7616ee19f12ef69cd50e02d230
      https://github.com/llvm/llvm-project/commit/5d47e7d768951a7616ee19f12ef69cd50e02d230
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-12-27 (Mon, 27 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

  Log Message:
  -----------
  [RISCV] Convert whole register copies as the source defined explicitly.

The implicit defines may come from a partial define in an instruction.
It does not mean the defining instruction and the COPY instruction have
the same vl and vtype. When the source comes from the implicit defines,
do not convert the whole register copies to vmv.v.v.

Differential Revision: https://reviews.llvm.org/D115866