[all-commits] [llvm/llvm-project] bb84dd: [AArch64] Add a tablegen pattern for RADDHN/RADDHN2.

[Alexandros Lamprineas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bb84dd81590bbcaa2277f7f15700ac842af8932e
      https://github.com/llvm/llvm-project/commit/bb84dd81590bbcaa2277f7f15700ac842af8932e
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-12-24 (Fri, 24 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/arm64-raddhn-combine.ll

  Log Message:
  -----------
  [AArch64] Add a tablegen pattern for RADDHN/RADDHN2.

Converts RSHRN/RSHRN2 to RADDHN/RADDHN2 when the shift amount is half
the width of the vector element. The latter has twice the throughput
and half the latency on Arm out-of-order cores. Setting up the zero
register adds no latency.

Differential Revision: https://reviews.llvm.org/D116166