[all-commits] [llvm/llvm-project] e70ef6: [AArch64] Add a tablegen pattern for SQXTN2.

[Alexandros Lamprineas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e70ef6d9245e0f5497f34d9f10958a15be0cceed
      https://github.com/llvm/llvm-project/commit/e70ef6d9245e0f5497f34d9f10958a15be0cceed
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-12-23 (Thu, 23 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/arm64-sqxtn2-combine.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll

  Log Message:
  -----------
  [AArch64] Add a tablegen pattern for SQXTN2.

Converts concat_vectors(Vd, trunc(smin(smax Vm, -2^n), 2^n-1) to
sqxtn2(Vd, Vm). Deliberately not handling v2i64 ~> v2i32 as the
min/max nodes are not legal (same thing we did for the SQXTN
patterns in https://reviews.llvm.org/D103263).

Differential Revision: https://reviews.llvm.org/D116105