[all-commits] [llvm/llvm-project] a9486a: [RISCV] Disable interleaving scalar loops in the l...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9486a40f7d18115682737b912f550ceef9b7d8d
      https://github.com/llvm/llvm-project/commit/a9486a40f7d18115682737b912f550ceef9b7d8d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-23 (Thu, 23 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll

  Log Message:
  -----------
  [RISCV] Disable interleaving scalar loops in the loop vectorizer.

The loop vectorizer can interleave scalar loops even if it doesn't
vectorize them. I don't believe we intended to enable this when
we enabled interleaving for vector instructions.

Disable interleaving for VF=1 like X86 and AMDGPU already do. Test
lifted from AMDGPU.

Differential Revision: https://reviews.llvm.org/D115975