[all-commits] [llvm/llvm-project] d28630: GlobalISel: Regen vector mir tests, add tests for ...
petar-avramovic via All-commits
all-commits at lists.llvm.org
Thu Dec 23 05:30:34 PST 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: d2863088ab8996169f1f4ff22b59066200c856e5
https://github.com/llvm/llvm-project/commit/d2863088ab8996169f1f4ff22b59066200c856e5
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2021-12-23 (Thu, 23 Dec 2021)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
Log Message:
-----------
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
Precommit for D114198 (Rework more/fewer elements for vectors).
Regenerate auto-generated mir tests for vectors (use CHECK-NEXT instead
of CHECK). Remove -global-isel-abort=0 where it is no longer needed.
Add mir tests for different AMDGPU sub-targets and they way they lower
function vector arguments (tests for legalization artifact combiner).
Commit: 29f88b93fdbe3e20c35842ca3a6c2a3f1a81cfce
https://github.com/llvm/llvm-project/commit/29f88b93fdbe3e20c35842ca3a6c2a3f1a81cfce
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2021-12-23 (Thu, 23 Dec 2021)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-atomics.ll
M llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel] Rework more/fewer elements for vectors
Artifact combiner is not able to access individual elements after using
LCMTy style merge/unmerge, extract and insert to change vector number of
elements (pad with undef or split to sub-vector instructions).
Use unmerge to individual elements instead and then merge elements into
requested types.
Change argument lowering for vectors and moreElementsVector to use
buildPadVectorWithUndefElements and buildDeleteTrailingVectorElements.
FewerElementsVector had a few helpers that had different behavior,
introduce new helper for most of the opcodes.
FewerElementsVector helper is more flexible since it can create leftover
instruction smaller then requested type (useful in case target wants to
avoid pad with undef and use fewer registers). If target does not want
leftover of different type it should call more elements first.
Some helpers were performing more elements first to have split without
leftover. Opcodes that used this helper use clampMaxNumElementsStrict
(does more elements first) in LegalizerInfo to avoid test changes.
Fixes failures caused by failing to combine artifacts created during
more/fewer elements vector.
Differential Revision: https://reviews.llvm.org/D114198
Compare: https://github.com/llvm/llvm-project/compare/3d36da77020b...29f88b93fdbe
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