[all-commits] [llvm/llvm-project] 907500: [AMDGPU] Move call clobbered return address regist...

Wed Dec 22 07:21:29 PST 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9075009d1fd5f2bf9aa6c2f362d2993691a316b3
      https://github.com/llvm/llvm-project/commit/9075009d1fd5f2bf9aa6c2f362d2993691a316b3
  Author: RamNalamothu <VenkataRamanaiah.Nalamothu at amd.com>
  Date:   2021-12-22 (Wed, 22 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
    M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
    M llvm/test/CodeGen/AMDGPU/fpow.ll
    M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/ipra.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/nested-calls.ll
    M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
    M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
    M llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
    M llvm/test/CodeGen/AMDGPU/save-fp.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir

  Log Message:
  -----------
  [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

Currently the return address ABI registers s[30:31], which fall in the call
clobbered register range, are added as a live-in on the function entry to
preserve its value when we have calls so that it gets saved and restored
around the calls.

But the DWARF unwind information (CFI) needs to track where the return address
resides in a frame and the above approach makes it difficult to track the
return address when the CFI information is emitted during the frame lowering,
due to the involvment of understanding the control flow.

This patch moves the return address ABI registers s[30:31] into callee saved
registers range and stops adding live-in for return address registers, so that
the CFI machinery will know where the return address resides when CSR
save/restore happen during the frame lowering.

And doing the above poses an issue that now the return instruction uses undefined
register `sgpr30_sgpr31`. This is resolved by hiding the return address register
use by the return instruction through the `SI_RETURN` pseudo instruction, which
doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the
`S_SETPC_B64_return` during the `expandPostRAPseudo()`.

As an added benefit, this patch simplifies overall return instruction handling.

Note: The AMDGPU CFI changes are there only in the downstream code and another
version of this patch will be posted for review for the downstream code.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D114652