[all-commits] [llvm/llvm-project] 19727e: [AMDGPU] Enable divergence predicates for ctlz/cttz

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8
      https://github.com/llvm/llvm-project/commit/19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    A llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll

  Log Message:
  -----------
  [AMDGPU] Enable divergence predicates for ctlz/cttz

ctlz/cttz get lowered to the set of target opcodes
This change enables the ISel to select SALU or VALU form according to the SDNode divergence.
CTLZ - S_FLBIT_I32_B32 if uniform and V_FFBH_U32_e64 if divergent
CTTZ - S_FF1_I32_B32   if uniform and V_FFBL_B32_e64 if divergent
Also @llvm.amdgcn.sffbh.i32 gets lowered to S_FLBIT_I32 if uniform and V_FFBH_I32_e64 if divergent
NOTE: 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B64 are not currently supported by the DAG ISel.
ctlz/cttz with i64 input are split into two 32bit instructions. Nevertheless, they already have the patterns
and were equipped with the divergence predicates to make sure they will be selected correctly when enabled.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D116044