[all-commits] [llvm/llvm-project] 7e44eb: [AArch64][SVE] Improve code generation for VLS i1 ...

[David Truby via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e44eb079d99ce1b9b2e2f8f3cf1b7f4211d7b85
      https://github.com/llvm/llvm-project/commit/7e44eb079d99ce1b9b2e2f8f3cf1b7f4211d7b85
  Author: David Truby <david.truby at arm.com>
  Date:   2021-12-17 (Fri, 17 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    A llvm/test/CodeGen/AArch64/sve-punpklo-combine.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve code generation for VLS i1 masks

This patch partially resolves an issue for VLS code generation
where a mask is generated from a smaller width integer comparison
than the instruction using the mask requires.

Instead of sign extending a p register by converting it to a z
register, extending that, and converting back, we instead just
do an unpack of the p register.

A separate issue causes the code generation to still be poor when
the mask generation would fit in a neon register, as we then use
a neon comparison operation and have to convert that to a p register.
This will be resolved in a separate patch.

Reviewed By: peterwaller-arm

Differential Revision: https://reviews.llvm.org/D111221