[all-commits] [llvm/llvm-project] a640f1: [X86] combineAnd - don't demand operand vector ele...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a640f16ca2da46bb5fcd522d2130234a41e157e9
      https://github.com/llvm/llvm-project/commit/a640f16ca2da46bb5fcd522d2130234a41e157e9
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-12-16 (Thu, 16 Dec 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-partial-undef.ll
    M llvm/test/CodeGen/X86/vector-trunc-math.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll

  Log Message:
  -----------
  [X86] combineAnd - don't demand operand vector elements if the other operand element is zero

If either operand has a zero element, then we don't need the equivalent element from the other operand, as no bits will be set.