[all-commits] [llvm/llvm-project] cce93b: [MachineVerifier] Undef subreg operands do not req...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cce93b339724a34928f0630fa8ed6b09b4ba753b
      https://github.com/llvm/llvm-project/commit/cce93b339724a34928f0630fa8ed6b09b4ba753b
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2021-12-16 (Thu, 16 Dec 2021)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir

  Log Message:
  -----------
  [MachineVerifier] Undef subreg operands do not require subranges

D112556 added verification that the live interval for a subreg operand
must have subranges. This patch fixes a corner case, where if all subreg
operands for a particular register are undef uses then no subranges
are required. This matches how LiveIntervalCalc would build the live
intervals in the first place, since an undef use is not considered
to read the register.

Before this patch, CodeGen/AMDGPU/no-remat-indirect-mov.mir would fail
with -early-live-intervals:

 # After Live Interval Analysis
...
*** Bad machine code: Live interval for subreg operand has no subranges ***
- function:    index_vgpr_waterfall_loop
- basic block: %bb.1  (0x6a9a968) [352B;496B)
- instruction: 432B	%24:vgpr_32 = V_MOV_B32_e32 undef %18.sub0:vreg_512, implicit $exec, implicit %18:vreg_512, implicit $m0
- operand 1:   undef %18.sub0:vreg_512

Differential Revision: https://reviews.llvm.org/D115360