[all-commits] [llvm/llvm-project] d3c2ad: [RISCV] Fix whole vector register move instruction...

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3c2ad154ec8bcea0a4ac602bc17e5d9d4cdd27f
      https://github.com/llvm/llvm-project/commit/d3c2ad154ec8bcea0a4ac602bc17e5d9d4cdd27f
  Author: jacquesguan <jacquesguan at me.com>
  Date:   2021-12-16 (Thu, 16 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/invalid.s

  Log Message:
  -----------
  [RISCV] Fix whole vector register move instruction's vector register constraint.

According to the v-spec, the source and destination VR of vmv<nr>r.v should be aligned for the VR group size.

Differential Revision: https://reviews.llvm.org/D115720