[all-commits] [llvm/llvm-project] cce4a7: [compiler-rt][AArch64] Add a workaround for Exynos...

[stephenhines via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cce4a7258b81159e57a411896011ee2742f17def
      https://github.com/llvm/llvm-project/commit/cce4a7258b81159e57a411896011ee2742f17def
  Author: Stephen Hines <srhines at google.com>
  Date:   2021-12-14 (Tue, 14 Dec 2021)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model.c

  Log Message:
  -----------
  [compiler-rt][AArch64] Add a workaround for Exynos 9810

Big.LITTLE Heterogeneous architectures, as described by ARM [1],
require that the instruction set architecture of the big and little
cores be compatible. However, the Samsung Exynos 9810 is known to
have different ISAs in its core.
According to [2], some cores are ARMv8.2 and others are ARMv8.0.

Since LSE is for ARMv8.1 and later, it should be disabled
for this broken CPU.

[1] https://developer.arm.com/documentation/den0024/a/big-LITTLE-Technology
[2] https://github.com/golang/go/issues/28431

Patch by: Byoungchan Lee (byoungchan.lee at gmx.com)
Reviewed By: srhines

Differential Revision: https://reviews.llvm.org/D114523