[all-commits] [llvm/llvm-project] 392689: [RISCV] Add isel support for scalar STRICT_FADD/FS...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3926893439c419055b43df4f37db354cde3d02c2
      https://github.com/llvm/llvm-project/commit/3926893439c419055b43df4f37db354cde3d02c2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-14 (Tue, 14 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    A llvm/test/CodeGen/RISCV/double-arith-strict.ll
    A llvm/test/CodeGen/RISCV/float-arith-strict.ll
    A llvm/test/CodeGen/RISCV/half-arith-strict.ll

  Log Message:
  -----------
  [RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.

Test that STRICT_FMINNUM/FMAXNUM are lowered to libcalls for f32/f64.
The RISC-V instructions don't match the behavior of fmin/fmax libcalls
with respect to SNaN.

Promoting FMINNUM/FMAXNUM for f16 needs more work outside of the
RISC-V backend.

Reviewed By: asb, arcbbb

Differential Revision: https://reviews.llvm.org/D115680