[all-commits] [llvm/llvm-project] 7598ac: [RISCV] Convert (splat_vector (load)) to vlse with...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7598ac5ec5a6bebc347ce95daf3be7a62ab2888e
      https://github.com/llvm/llvm-project/commit/7598ac5ec5a6bebc347ce95daf3be7a62ab2888e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-14 (Tue, 14 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll

  Log Message:
  -----------
  [RISCV] Convert (splat_vector (load)) to vlse with 0 stride.

We already do this for splat nodes that carry a VL, but not for
splats that use VLMAX.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D115483