[all-commits] [llvm/llvm-project] 61bb8b: [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)

[Alexandros Lamprineas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 61bb8b5d404023d5cd329a6d56c2467a81ab138a
      https://github.com/llvm/llvm-project/commit/61bb8b5d404023d5cd329a6d56c2467a81ab138a
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-12-14 (Tue, 14 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
    M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
    M llvm/test/CodeGen/AArch64/arm64-vshr.ll
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
    M llvm/test/CodeGen/AArch64/div_minsize.ll
    M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll
    M llvm/test/CodeGen/AArch64/vselect-constants.ll

  Log Message:
  -----------
  [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)

CMLT has twice the execution throughput of SSHR on Arm out-of-order cores.

Differential Revision: https://reviews.llvm.org/D115457