[all-commits] [llvm/llvm-project] 65033e: [AArch64] Add a tablegen pattern for UZP1.

[Alexandros Lamprineas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65033ef9e8a6ecf7c2ad80c4e3e0c339b44e61b4
      https://github.com/llvm/llvm-project/commit/65033ef9e8a6ecf7c2ad80c4e3e0c339b44e61b4
  Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
  Date:   2021-12-14 (Tue, 14 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
    M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
    M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
    M llvm/test/CodeGen/AArch64/fcvt_combine.ll
    M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/neon-truncstore.ll

  Log Message:
  -----------
  [AArch64] Add a tablegen pattern for UZP1.

Converts concat_vectors(V64 (trunc V128), V64 (trunc V128)), which
would otherwise be lowered as xtn followed by xtn2, to uzp1.

Differential Revision: https://reviews.llvm.org/D115435