[all-commits] [llvm/llvm-project] aba437: [mlir][Vector] Patterns flattening vector transfer...

[bjacob via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aba437ceb2379f219935b98a10ca3c5081f0c8b7
      https://github.com/llvm/llvm-project/commit/aba437ceb2379f219935b98a10ca3c5081f0c8b7
  Author: Benoit Jacob <benoitjacob at google.com>
  Date:   2021-12-13 (Mon, 13 Dec 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.h
    M mlir/include/mlir/IR/BuiltinTypes.h
    M mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
    M mlir/lib/IR/BuiltinTypes.cpp
    A mlir/test/Dialect/Vector/vector-transfer-flatten.mlir
    M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp

  Log Message:
  -----------
  [mlir][Vector] Patterns flattening vector transfers to 1D

This is the second part of https://reviews.llvm.org/D114993 after slicing
into 2 independent commits.

This is needed at the moment to get good codegen from 2d vector.transfer
ops that aim to compile to SIMD load/store instructions but that can
only do so if the whole 2d transfer shape is handled in one piece, in
particular taking advantage of the memref being contiguous rowmajor.

For instance, if the target architecture has 128bit SIMD then we would
expect that contiguous row-major transfers of <4x4xi8> map to one SIMD
load/store instruction each.

The current generic lowering of multi-dimensional vector.transfer ops
can't achieve that because it peels dimensions one by one, so a transfer
of <4x4xi8> becomes 4 transfers of <4xi8>.

The new patterns here are only enabled for now by
 -test-vector-transfer-flatten-patterns.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D114993