[all-commits] [llvm/llvm-project] 2e585d: [AArch64][SVE] Lower vector.insert to predicated m...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e585dd91a87d15cd68b4a3f63ffb15800c13bc8
      https://github.com/llvm/llvm-project/commit/2e585dd91a87d15cd68b4a3f63ffb15800c13bc8
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2021-12-13 (Mon, 13 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/split-vector-insert.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll

  Log Message:
  -----------
  [AArch64][SVE] Lower vector.insert to predicated merged MOV

Use predicated SEL for vector.insert instead of going through memory

Differential Revision: https://reviews.llvm.org/D115259