[all-commits] [llvm/llvm-project] 80ed2f: [RISCV] Share tablegen classes for F, D, and Zfh. ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80ed2f6b3659d7d9449517a0eb552f361ce80e15
      https://github.com/llvm/llvm-project/commit/80ed2f6b3659d7d9449517a0eb552f361ce80e15
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-10 (Fri, 10 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Share tablegen classes for F, D, and Zfh. Other simplifications. NFC

By adding the register class and funct as template parameters we
can share the classes with all 3 extensions.

I've used "let SchedRW =" to avoid repeating scheduler classes on
multiple lines where we previously inherited from the Sched class.

A subsequent patch will add mayRaiseFPException and FRM dependencies.
Reducing the number of classes means less repeating for those changes.

This of course conflicts with the Zfinx patch D93298.

Reviewed By: achieveartificialintelligence

Differential Revision: https://reviews.llvm.org/D115469