[all-commits] [llvm/llvm-project] cf58b9: [AMDGPU] Add AV class spill pseudo instructions

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf58b9ce98043d4c9af5ffb5b47a18009b145b5b
      https://github.com/llvm/llvm-project/commit/cf58b9ce98043d4c9af5ffb5b47a18009b145b5b
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-12-10 (Fri, 10 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    A llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    A llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll

  Log Message:
  -----------
  [AMDGPU] Add AV class spill pseudo instructions

While enabling vector superclasses with D109301,
the AV spills are converted into VGPR spills by
introducing appropriate copies. The whole thing
ended up adding two instructions per spill (a copy
+ vgpr spill pseudo) and caused an incorrect
liverange update during inline spiller.

This patch adds the pseudo instructions for all
AV spills from 32b to 1024b and handles them in
the way all other spills are lowered.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D115439