[all-commits] [llvm/llvm-project] 39c861: [RISCV] Fix vm operand constraint to fit GCC's beh...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 39c861719bc84fb2f09c490752c0da8d0e9207da
      https://github.com/llvm/llvm-project/commit/39c861719bc84fb2f09c490752c0da8d0e9207da
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2021-12-09 (Thu, 09 Dec 2021)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

  Log Message:
  -----------
  [RISCV] Fix vm operand constraint to fit GCC's behavior

- `vm` constraint is used for masking operand, which always v0.

- Update testcase, only masking operand should use `vm`, vector mask operations
  should just use `vr` for any vector register.

 - Revise the description of `vm` constraint.

- This patch also fix issue on RISCVRegisterInfo.td and RISCVISelLowering.cpp.

  RISCVRegisterInfo.td:
  - The first VT in the list must be the largest total size since the
    SelectionDAGBuilder uses the first register in the list as the canonical
    type for the register.

  RISCVISelLowering.cpp:
  - Fix RISCVTargetLowering::splitValueIntoRegisterParts and
    RISCVTargetLowering::joinRegisterPartsIntoValue for handling vectors
    with different total size, that will happened on fractional LMUL since
    fractional LMUL is always occupy one vector register.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D112599