[all-commits] [llvm/llvm-project] 01bc67: [SVE][InstCombine] Support more cases where ld1/st...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 01bc67e449a91d05d20d36630c9fb99573339ec4
      https://github.com/llvm/llvm-project/commit/01bc67e449a91d05d20d36630c9fb99573339ec4
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2021-12-08 (Wed, 08 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll

  Log Message:
  -----------
  [SVE][InstCombine] Support more cases where ld1/st1 can be lowered to load/store instructions.

This patch extends the "is all active predicate" check to cover
cases where the predicate is casted but in a way that doesn't
change its "all active" status.

Differential Revision: https://reviews.llvm.org/D115047