[all-commits] [llvm/llvm-project] f0f6bb: [MIPS] Add FPU Delay Slot for MIPS1/2/3

[Djordje Todorovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f0f6bba5b285632577fd77aa802b07d927f2573e
      https://github.com/llvm/llvm-project/commit/f0f6bba5b285632577fd77aa802b07d927f2573e
  Author: Djordje Todorovic <djordje.todorovic at syrmia.com>
  Date:   2021-12-07 (Tue, 07 Dec 2021)

  Changed paths:
    M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.h
    M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
    M llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll

  Log Message:
  -----------
  [MIPS] Add FPU Delay Slot for MIPS1/2/3

MIPS I, II, and III have delay slots for floating point
comparisons and floating point register transfers (mtc1, mfc1).
Currently, these are not taken into account and thus broken code
may be generated on these targets. This patch inserts nops
as necessary, while attempting to leave the current instruction
if it is safe to stay.

The tests in this patch were updated by @sajattack

Patch by @overdrivenpotato (Marko Mijalkovic <marko.mijalkovic97 at gmail.com>)

Differential Revision: https://reviews.llvm.org/D115127