[all-commits] [llvm/llvm-project] acdbd3: [RISCV] Loosen some restrictions on lowering const...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acdbd34cfb810a0587e17bfb4afc66b6b55f25ba
      https://github.com/llvm/llvm-project/commit/acdbd34cfb810a0587e17bfb4afc66b6b55f25ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-12-06 (Mon, 06 Dec 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

  Log Message:
  -----------
  [RISCV] Loosen some restrictions on lowering constant BUILD_VECTORs using vid.v.

The immediate size check on StepNumerator did not take into account
that vmul.vi does not exist. It also did not account for power of 2
constants that can be done with vshl.vi.

This patch fixes this by moving the conversion from mul to shift
further up. Then we can consider the immediates separately for MUL
vs SHL. For MUL I've allowed simm12 which requires a single addi
before a vmul.vx. For SHL I've allowed any uimm5 which works with
vshl.vi. We could relax these further in the future. This is a
starting point that allows us to emit the same number of instructions
we were already using for smaller numerators.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D115081