[all-commits] [llvm/llvm-project] a6f751: [AArch64][SVE] Fix ICE extracting fixedvec from sc...

[Peter Waller via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6f751c34ec1ead6fe94c5eea375307fc12a5359
      https://github.com/llvm/llvm-project/commit/a6f751c34ec1ead6fe94c5eea375307fc12a5359
  Author: Peter Waller <peter.waller at arm.com>
  Date:   2021-12-06 (Mon, 06 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

  Log Message:
  -----------
  [AArch64][SVE] Fix ICE extracting fixedvec from scalable load

f526c600c043 had a concern raised because of an invalid typesize request
on a scalable vector, which this patch addresses.

Prevent shouldReduceLoadWidth from attempting to query the bit size, and
add a regression test in sve-extract-fixed-vector.ll.

Differential Revision: https://reviews.llvm.org/D115156