[all-commits] [llvm/llvm-project] 9f95bc: [clang][ARM] relax -mtp=cp15 for non-thumb cases

Nick Desaulniers via All-commits all-commits at lists.llvm.org
Fri Dec 3 14:21:42 PST 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f95bc7dc18390199553cf2ea3bfcdc6a95717ef
  Author: Nick Desaulniers <ndesaulniers at google.com>
  Date:   2021-12-03 (Fri, 03 Dec 2021)

  Changed paths:
    M clang/lib/Driver/ToolChains/Arch/ARM.cpp
    M clang/lib/Driver/ToolChains/Arch/ARM.h
    M clang/test/Driver/clang-translation.c

  Log Message:
  [clang][ARM] relax -mtp=cp15 for non-thumb cases

Building -march=armv6k Linux kernels with -mtp=cp15 fails to

error: hardware TLS register is not supported for the arm

@ardb found docs for ARM1176JZF-S (ARMv6K) that reference hard thread

Relax our ARMv6 check for cases where we're targeting ARM via -marm (vs
Thumb1 via -mthumb).  This more closely matches the KConfig requirements
for where we plan to use these (ie. ARMv6K, ARMv7 (arm or thumb2)).

As @peter.smith mentions:
  on armv5 we can write the instruction to read/write to CP15 C13 with
  the ThreadID opcode. However on no armv5 implementation will the CP15
  C13 have a Thread ID register. The GCC intent seems to be whether the
  instruction is encodable rather than check what the CPU supports.

Link: https://github.com/ClangBuiltLinux/linux/issues/1502
Link: https://developer.arm.com/documentation/ddi0301/h/system-control-coprocessor/system-control-processor-registers/c13--thread-and-process-id-registers

Reviewed By: ardb, peter.smith

Differential Revision: https://reviews.llvm.org/D114116

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