[all-commits] [llvm/llvm-project] d6c0ef: [PowerPC] Handle base load with reservation mnemonic

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d6c0ef78876dc3204b0a6d92119b15aa9cd12af3
      https://github.com/llvm/llvm-project/commit/d6c0ef78876dc3204b0a6d92119b15aa9cd12af3
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2021-12-03 (Fri, 03 Dec 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/test/CodeGen/PowerPC/inline-asm-label.ll
    M llvm/test/MC/PowerPC/ppc64-encoding-bookII.s
    M llvm/test/MC/PowerPC/ppc64-errors.s

  Log Message:
  -----------
  [PowerPC] Handle base load with reservation mnemonic

The Power ISA defined l[bhwdq]arx as both base and
extended mnemonics. The base mnemonic takes the EH
bit as an operand and the extended mnemonic omits
it, making it implicitly zero. The existing
implementation only handles the base mnemonic when
EH is 1 and internally produces a different
instruction. There are historical reasons for this.
This patch simply removes the limitation introduced
by this implementation that disallows the base
mnemonic with EH = 0 in the ASM parser.

This resolves an issue that prevented some files
in the Linux kernel from being built with
-fintegrated-as.

Also fix a crash if the value is not an integer immediate.