[all-commits] [llvm/llvm-project] b8f1cc: [ARM] Introduce i8neg and i8pos addressing modes

David Green via All-commits all-commits at lists.llvm.org
Thu Dec 2 09:10:40 PST 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b8f1ccb0acf8dccdd3fb706465ec958763987bee
  Author: David Green <david.green at arm.com>
  Date:   2021-12-02 (Thu, 02 Dec 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMFrameLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
    M llvm/test/CodeGen/Thumb2/postinc-distribute.mir

  Log Message:
  [ARM] Introduce i8neg and i8pos addressing modes

Some instructions with i8 immediate ranges can only hold negative values
(like t2LDRHi8), only hold positive values (like t2STRT) or hold +/-
depending on the U bit (like the pre/post inc instructions. e.g
t2LDRH_POST). This patch splits the AddrModeT2_i8 into AddrModeT2_i8,
AddrModeT2_i8pos and AddrModeT2_i8neg to make this clear.

This allows us to get the offset ranges of t2LDRHi8 correct in the
load/store optimizer, fixing issues where we could end up creating
instructions with positive offsets (which may then be encoded as ldrht).

Differential Revision: https://reviews.llvm.org/D114638

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