[all-commits] [llvm/llvm-project] 399b7d: [AMDGPU] Add a regclass flag for scalar registers

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 399b7de0ea34cdf2d54ee874a2d0f6e595b960d4
      https://github.com/llvm/llvm-project/commit/399b7de0ea34cdf2d54ee874a2d0f6e595b960d4
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-12-01 (Wed, 01 Dec 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td

  Log Message:
  -----------
  [AMDGPU] Add a regclass flag for scalar registers

Along with vector RC flags, this scalar flag will
make various regclass queries like `isVGPR` more
accurate.

Regclasses other than vectors are currently set
with the new flag even though certain unallocatable
classes aren't truly scalars. It would be ok as long
as they remain unallocatable.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D110053