[all-commits] [llvm/llvm-project] 617ad1: [SelectionDAG] Add pattern to haveNoCommonBitsSet

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 617ad14060dcdfa9f1f967a3edd9e097de8bf83a
      https://github.com/llvm/llvm-project/commit/617ad14060dcdfa9f1f967a3edd9e097de8bf83a
  Author: Omer Aviram <omeraviram1 at gmail.com>
  Date:   2021-12-01 (Wed, 01 Dec 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/or-lea.ll
    M llvm/test/CodeGen/X86/vec_no-common-bits.ll

  Log Message:
  -----------
  [SelectionDAG] Add pattern to haveNoCommonBitsSet

Correctly identify the following pattern, which has no common bits: (X & ~M) op (Y & M).

Differential Revision: https://reviews.llvm.org/D113970