[all-commits] [llvm/llvm-project] 050c33: [PowerPC] Replace MFVSRLD with MFVSRD when the vec...

[stefanp-ibm via All-commits]

  Branch: refs/heads/stefanp/ConvertMFVSRLD
  Home:   https://github.com/llvm/llvm-project
  Commit: 050c335ab42f96acfdfa6572cad1310e685cd199
      https://github.com/llvm/llvm-project/commit/050c335ab42f96acfdfa6572cad1310e685cd199
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2021-11-26 (Fri, 26 Nov 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
    M llvm/test/CodeGen/PowerPC/vector-reduce-add.ll

  Log Message:
  -----------
  [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical

The MFVSRD is faster than the MFVSRLD instruction and if the input vector is
symmetrical then both instructions produce the same result and we should prefer
the faster one.

WIP.