[all-commits] [llvm/llvm-project] 08d45e: [AArch64][SVEIntrinsicOpts] Fix: predicated SVE mu...

[Igor Kirillov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 08d45e6f4da03836dc2380b7bae650ae80cfae35
      https://github.com/llvm/llvm-project/commit/08d45e6f4da03836dc2380b7bae650ae80cfae35
  Author: Igor Kirillov <Igor.Kirillov at arm.com>
  Date:   2021-11-26 (Fri, 26 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll

  Log Message:
  -----------
  [AArch64][SVEIntrinsicOpts] Fix: predicated SVE mul/fmul are not commutative

We can not swap multiplicand and multiplier because the sve intrinsics
are predicated. Imagine lanes in vectors having the following values:
         pg = 0
         multiplicand = 1 (from dup)
         multiplier = 2
The resulting value should be 1, but if we swap multiplicand and multiplier it will become 2,
which is incorrect.

Differential Revision: https://reviews.llvm.org/D114577