[all-commits] [llvm/llvm-project] 3cf4a2: [DAG] SimplifyDemandedBits - simplify rotl/rotr to...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3cf4a2c6203b5777d56f0c04fb743b85a041d6f9
      https://github.com/llvm/llvm-project/commit/3cf4a2c6203b5777d56f0c04fb743b85a041d6f9
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-11-24 (Wed, 24 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/test/CodeGen/X86/rotate_vec.ll
    M llvm/test/CodeGen/X86/vector-rotate-128.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-rotate-512.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srl

If we only demand bits from one half of a rotation pattern, see if we can simplify to a logical shift.

For the ARM rev16 patterns, I had to drop a fold to prevent srl(bswap()) -> rotr(bswap) -> srl(bswap) infinite loops. I've replaced this with an isel PatFrag which should do the same task.

https://alive2.llvm.org/ce/z/iroxki (rol -> shl by amt iff demanded bits has at least as many trailing zeros as the shift amount)
https://alive2.llvm.org/ce/z/4ez_U- (ror -> shl by revamt iff demanded bits has at least as many trailing zeros as the reverse shift amount)
https://alive2.llvm.org/ce/z/cD7dR- (ror -> lshr by amt iff demanded bits has at least as many leading zeros as the shift amount)
https://alive2.llvm.org/ce/z/_XGHtQ (rol -> lshr by revamt iff demanded bits has at least as many leading zeros as the reverse shift amount)

Differential Revision: https://reviews.llvm.org/D114354