[all-commits] [llvm/llvm-project] 9e03e8: [AMDGPU] Enable fneg and fabs divergence-driven in...

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e03e8c99ec57e91cd146dfaa6c5cadde4600d32
      https://github.com/llvm/llvm-project/commit/9e03e8c99ec57e91cd146dfaa6c5cadde4600d32
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2021-11-23 (Tue, 23 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
    A llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f64.ll

  Log Message:
  -----------
  [AMDGPU] Enable fneg and fabs divergence-driven instruction selection.

Detailed description: We currently have a set of patterns to select ISD::FNEG and ISD::FABS to the bitwise operations.  We need to make them predicated to select the VALU or SALU bitwise operation variant according to the SDNode divergence bit.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D114257