[all-commits] [llvm/llvm-project] e7026a: [mlir][Vector] Thread 0-d vectors through ExtractE...

[Nicolas Vasilache via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7026aba004934cad5487256601af7690757d09f
      https://github.com/llvm/llvm-project/commit/e7026aba004934cad5487256601af7690757d09f
  Author: Nicolas Vasilache <nicolas.vasilache at gmail.com>
  Date:   2021-11-23 (Tue, 23 Nov 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/include/mlir/IR/OpBase.td
    M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir
    A mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir

  Log Message:
  -----------
  [mlir][Vector] Thread 0-d vectors through ExtractElementOp.

This revision starts making concrete use of 0-d vectors to extend the semantics of
ExtractElementOp.
In the process a new VectorOfAnyRank Tablegen OpBase.td is added to allow progressive transition to supporting 0-d vectors by gradually opting in.

Differential Revision: https://reviews.llvm.org/D114387